In semiconductor memory technology, DRAMs experienced rapid growth after the development of the one transistor memory cell structure by Dennard as disclosed in U.S. Pat. No. 3,387,286. The one transistor memory cell uses a capacitor for storing different amounts of charge to represent the distinguishable binary logic states. The early basic one transistor one capacitor memory cell structure utilized a planar access transistor and a planar capacitor in a nearly two dimensional structure. Of the various types of semiconductor memories, DRAMs have been the most widely produced because of their high density, low cost and fast performance.
The major driving force in DRAM design has always been density. It is recognized that the cell density of DRAM chips has approximately quadrupled for each new generation but that the chip area has increased only about 1.5 times per generation. As cells have shrunk in size over the years, various problems have arisen that needed to be dealt with. The following equation summarizes the basic signal level of the one-transistor one-capacitor cell: ##EQU1## where .DELTA.V is the differential sense signal, C.sub.S is the storage capacitance, C.sub.B is the parasitic bit line capacitance, V.sub.S is the storage node voltage, which is set to either the high-state, V.sub.H, or the low-state, V.sub.L, and V.sub.REF is the dummy (or reference) cell voltage. The second equality in the above equation, Eq. (1), holds when the reference voltage is set at its optimum value midway between V.sub.H and V.sub.L, i.e. V.sub.REF =(V.sub.H +V.sub.L)/2. As technology and design changes have increased the density of memory cells, consequent changes in one or more of the parameters in Eq. (1) have occurred, adversely affecting the performance of the cells.
For example, as cell sizes get smaller, the bit lines get closer together and the mutual capacitance between bit lines grows. Increased coupling between bit lines means that each bit line is increasingly affected by tile operation of its neighboring lines. Eventually a point is reached at which cell data cannot be read reliably because of that interference- One of the major challenges facing designers of DRAM chips is the problem of getting sufficient cell capacitance into the available cell area. A major effort has developed to fabricate three dimensional capacitor structures to solve this problem. Various-three dimensional designs have been studied such as, the stacked capacitor cell, the trench capacitor cell, substrate-plate trench capacitor cell, and the stacked in trench capacitor cell, some of which are shown in the following U.S. Patents: U.S. Pat. Nos. 5,089,868; 5,041,887; 4,978,364 and 4,833,094. While the three dimensional technology has enabled further reductions in cell size and hence increases in density, the problem of maintaining a sufficiently large storage capacitance, C.sub.S, obviously gets worse with each new generation, as technology scales down further. Furthermore, accompanying reductions in power supply voltage are necessary in order to maintain or improve reliability, and to reduce power. But reduction of supply voltage implies reduction of V.sub.H -V.sub.L in Eq. (1) thereby further diminishing already-small signal levels.
Dhong et al. in IBM TDB, Vol. 31, No. 7, Dec. 1988 disclose the incorporation of three dimensional capacitor technology in a cell design that increases signal strength. The cell is a two transistor one capacitor cell structure that utilizes a deep substrate plate trench storage capacitor in which one transistor is connected by a surface contact to the inner electrode of the capacitor and the other transistor is connected directly to the diffusion region formed in the substrate around the trench, which forms the outer electrode of the capacitor. The gates of each of the transistors are connected to a complementary pair of word lines and the drains of each transistor are connected to a complementary pair of bit lines. While the two transistor one capacitor cell of Dhong et al. is claimed to provide twice as large a sense signal than does a conventional one transistor cell using the same capacitor size, and also has the advantage of elimination of the need of a dummy cell, the density is adversely effected because of the utilization of two word lines for each cell. In addition, isolation between capacitors on the chip is provided by a pn junction in the substrate which, because of leakage, also compromises density since the cell capacitors cannot, therefore, be packed too closely.
An early version of a two transistor one capacitor cell is disclosed in Rideout et al. in IBM TDB, Vol. 20, No. 7, Dec. 1977 in which the source nodes of the transistors are connected to the electrodes of the storage capacitor while each of the drains are connected to a different bit line. Both of the gates of the transistors are connected to a single word line. The circuit, however, was very difficult to fabricate because of layout difficulties. In addition, because the design was planar, the added space needed for each cell was unacceptable.
With the emphasis in DRAM design always being on increasing density, the sense signals appearing on the bit lines inherently decreases. Measures must therefore be employed to ensure that the size of the sense signal will be adequate. Thus, there is a need to design a DRAM cell structure that would provide for adequate signal level while also allowing for high density.